I’m at the 15th Annual IEEE Hot Interconnects conference at Stanford today and every presentation so far has been an eye-opener. I’ll be blogging a lot of ideas from the conference this week, but I ...
Anthony Paul Bellezza the inventor of a 2D Graphene fusion process being used for CMOS Chip assembly processes, that fuses interconnects at temperatures within the thermal budget of the chip below 400 ...
DARPA, Intel, and Ayar Labs collaborate on developing 100-Tb/s-plus in-package silicon photonic interfaces. Ayar’s TeraPHY chiplet combines silicon photonics and CMOS in a flip-chip SiP. Thermal ...
Breakthrough CMOS device built on TeraSignal’s TSAFE™ analog front-end architecture integrates CMIS-based link training with Advanced Equalization to dramatically improve link margin, reach, and ...
A CMOS-compatible synthesis technology allows for the direct synthesis of graphene onto wafer-scale dielectric substrates at temperatures significantly below the CMOS thermal budget. All of this is ...
Silicon bonding technology promises optimized density, power efficiency, and performance In conjunction with Raytheon Vision Systems, wafer-bonding-process developer Ziptronix (Morrisville, NC) has ...
Avicena is showing ultra-fast microLED links operating at 14Gbps per lane as part of its LightBundle TM multi-Terabit interconnect technology MOUNTAIN VIEW, Calif. & BASEL, Switzerland--(BUSINESS WIRE ...
It's been 20 years since IBM first introduced copper interconnects in CMOS processing, sparking a minor revolution in the process. Within a handful of years, both Intel and AMD had made the jump as ...
Innovative CMOS Re-Driver for 800G Linear Pluggable Optical (LPO) Modules Reduces Power By Up to 50% and Adds Link Training and Diagnostics to Enable Mass Adoption of LPO Modules IRVINE, Calif. , ...
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