What is a Latch-up? Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either ...

A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of ...