Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...

SANTA CLARA, Calif.--(BUSINESS WIRE)--To further the adoption of NAND flash memory technology in the PC platform for an enhanced user experience, the Non-Volatile Memory Host Controller Interface ...

The diagram above by Rambus and Lumenci shows a Dual In-Line Memory Module (DIMM) which "is a module containing one or several Random Access Memory ('RAM') or Dynamic RAM ('DRAM') chips on a long, ...

DDR bus protocol allows signals to go idle, or tri-state, when they are not active. When debugging or performing JEDEC conformance measurements on the DDR interface, it is often necessary to perform ...

Today verification team are facing contradicting pressure, at one end they are asked to reduce the verification schedule while at other end the design complexity is increasing. To overcome the ...