Cadence 其Allegro 16.6 Package Designer与系统级封装(SiP)布局解决方案支持低端IC封装要求，满足新一代智能手机、平板电脑、超薄 ...

TEMPE, AZ--(Marketwire - Oct 22, 2012) - EPEPS -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced enhancements to its Allegro ® 16.6 ...

Santa Clara, Calif. — As chip designers, Kaushik Sheth and Egino Sarto struggled to fit silicon into cost-effective packages. Now they're trying to convince other chip designers to adopt a ...

Santa Cruz, Calif. — For most IC designers, package design must seem like a black art. It's a mysterious process far removed from chip design–until a problem develops and I/Os or bump patterns on the ...

Members can download this article in PDF format. Today, advances in semiconductors and ICs are producing ever smaller and denser circuits. With that comes the challenge of efficiently packaging and ...