SAN JOSE, Calif., Sept. 13, 2017 – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Conformal® Smart Logic Equivalence Checker (LEC), the next-generation equivalence checking ...

Designing a chip is a complex process. It starts with defining the architectural requirements, then microarchitecture development, followed by RTL design and functional verification. Then the design ...

SAN MATEO, Calif. - Formal equivalence checking is one of those silver bullets that comes along every so often in design flow evolution. It gives you the ability to transform a design from one level ...