The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...

Sun's engineers modeled a complex cache-coherence protocol, with parallelism and multi-threading, for a high-performance processor. They also used a commercial formal property-checking tool from ...

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...